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Pull requests: llvm/circt

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Pull requests list

[LLHD][Deseq] Lower reset-only async reset processes as register holds
#10344 opened Apr 28, 2026 by gipsyh Contributor Loading…
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1
[ImportVerilog] HierarchicalNames should skip reprocessing identical module instances
#10341 opened Apr 28, 2026 by rocallahan • Draft
[ImportVerilog] Capture analysis should skip reprocessing identical module instances
#10338 opened Apr 28, 2026 by rocallahan Loading…
[FIRRTL] InferDomains: On error, print more diagnostic information
#10337 opened Apr 27, 2026 by rwy7 Contributor Loading…
8
[SimToSV] lower sim.get_file to i32 fd
#10335 opened Apr 27, 2026 by nanjo712 Contributor Loading…
9
fix: update flattenIndices to generate correct indices for a flattened memref
#10327 opened Apr 25, 2026 by Abhilekhgautam Loading…
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1
[LLHD] Run Mem2Reg per slot to fix cubic scaling LLHD
#10321 opened Apr 25, 2026 by fabianschuiki Contributor Loading…
1
4
[Support] Add SparseOpSCC utility
#10305 opened Apr 23, 2026 by fzi-hielscher Contributor • Draft
13
[OM] Clean up ObjectOfieldOp: Move away from symbols, remove a field path and VerifyObjectFields pass
#10303 opened Apr 23, 2026 by uenoku Member Loading…
1
3
[FIRRTL] Eliminate Implicit Truncation
#10294 opened Apr 21, 2026 by darthscsi Contributor Loading…
16
[OM] Introduce explicit evaluator state and op patterns
#10265 opened Apr 18, 2026 by uenoku Member • Draft
1
14
[LowerToHW] Avoid "assert/assume/cover" string comparison, refactor label creation, NFC
#10251 opened Apr 17, 2026 by uenoku Member Loading…
[CellIFT] Add CellIFT instrumentation pass for HW/Comb/Seq IR
#10250 opened Apr 17, 2026 by flaviens Loading…
44
Plumb dbg.variable anchors into SMT symbol names
#10237 opened Apr 16, 2026 by 5iri Contributor Loading…
6
Add union roundtrip
#10236 opened Apr 16, 2026 by jpienaar Member Loading…
2
ImportVerilog: fix signedness propagation in ConversionExpression lowering
#10235 opened Apr 16, 2026 by kaituo-crypto Loading…
2
[Synth] Make FunctionalReduction runnable on any op
#10230 opened Apr 15, 2026 by SmitVaishnav Contributor Loading…
3
[FIRRTL][LowerLayers] Add probe type support
#10223 opened Apr 15, 2026 by prithayan Contributor Loading…
1
[Sim] Add cascade erase for print/proc.print format/get_file producer chains
#10204 opened Apr 14, 2026 by nanjo712 Contributor Loading…
4
[Synth][CutRewriter] Add timing-preserving area-flow reselection
#10193 opened Apr 13, 2026 by uenoku Member • Draft
5
[SSP] Reimplement auxiliary dependences without symbols
#10189 opened Apr 12, 2026 by jopperm Contributor Loading…
1
don't emit redundant write_en = 0 for seq_mem
#10174 opened Apr 10, 2026 by Abhilekhgautam Loading…
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2
[Moore][ImportVerilog] Implement static $cast via materializeConversion ImportVerilog
#10156 opened Apr 8, 2026 by sunhailong2001 Contributor Loading…
15
[FIRRTLToHW] Lower FIRRTL prints to Sim
#10153 opened Apr 8, 2026 by nanjo712 Contributor Loading…
2
[FIRRTLToHW] Lower firrtl.attach to new hw.attach and migrate SV-specific lowering logic to HWToSV.
#10138 opened Apr 6, 2026 by nanjo712 Contributor Loading…
6
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