[ImportVerilog] HierarchicalNames should skip reprocessing identical module instances#10341
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rocallahan wants to merge 1 commit intollvm:mainfrom
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[ImportVerilog] HierarchicalNames should skip reprocessing identical module instances#10341rocallahan wants to merge 1 commit intollvm:mainfrom
HierarchicalNames should skip reprocessing identical module instances#10341rocallahan wants to merge 1 commit intollvm:mainfrom
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…l module instances Currently `HierarchicalNames` unconditionally descends into all module instance bodies. This forces slang to instantiate complete ASTs for all module instances, transitively. For large designs this does not scale. For example with one 7M LOC Verilog example, ImportVerilog consumes more than 200GB of memory before crashing with OOM. So, use slang's canonical module bodies to avoid re-traversing identical modules. With this fixed on top of PR llvm#10338, the aforementioned example is imported quite quickly, consuming no more than 30GB of memory.
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Currently
HierarchicalNamesunconditionally descends into all module instance bodies. This forces slang to instantiate complete ASTs for all module instances, transitively. For large designs this does not scale. For example with one 7M LOC Verilog example, ImportVerilog consumes more than 200GB of memory before crashing with OOM.So, use slang's canonical module bodies to avoid re-traversing identical modules.
With this fixed on top of PR #10338, the aforementioned example is imported quite quickly, consuming no more than 30GB of memory.
NOTE: do not merge, this depends on PR #10338 being merged first. Also, I'm not super confident that the logic is correct yet.