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[ImportVerilog] Capture analysis should skip reprocessing identical module instances (#10338)
Currently capture analysis unconditionally descends into all module instance
bodies. This forces slang to instantiate complete ASTs for all module
instances, transitively. For large designs this does not scale. For example
with one 7M LOC Verilog example, ImportVerilog consumes more than 200GB of
memory before crashing with OOM.
Slang lets clients avoid this problem via "canonical instance bodies"
that express deduplication. Setting `VisitCanonical` to true in the
`ASTVisitor` template causes the `InstanceBodySymbol` visit to use
the deduplicated canonical instance body (when available). For this
analysis we don't need to re-analyze duplicate instance so we can
just keep track of which bodies we've visited and avoid descending
into already-visited bodies.1 parent 2123093 commit e9d6aed
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